1位二进制全加器： 先做一个底层设计： library ieee; use ieee.std_logic_1164.all; entity or2a is port(a,b:in std_logic; c:out std_logic): end; architecture one of or2a is begin c<=a or b; end； 然后是顶层设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder IS PORT ( ain,bin,cin :IN STD_LOGIC; cout, sum :OUT STD_LOGIC); END ENTITY f_adder; ARCHITECTURE fa1 OF f_adder IS COMPONENT h_adder PORT (a,b:IN STD_LOGIC; co,so :OUT STD_LOGIC); END COMPONENT ; COMPONENT or2a PORT (a,b: IN STD_LOGIC; c: OUT STD_LOGIC); END COMPONENT ; SIGNAL d,e,f :STD_LOGIC ; BEGIN u1 : h_adder PORT MAP (a=>ain,b=>bin,co=>d,so=>e) ; u2 : h_adder PORT MAP (a=>e,b=>cin,co=>f,so=>sum) ; u3 : or2a PORT MAP (a=>d,b=>f,c=>cout) ; END ARCHITECTURE fa1； 注意元件例化，要打包底层设计