library ieee;

use ieee.std_logic_1164.all;

entity decode3_8 is

port ( din : in std_logic_vector (2 downto 0);

en : in std_logic;

xout : out std_logic_vector (7 downto 0));

end decode3_8;

architecture one of decode3_8 is

begin

process (din, en)

begin

if en = '1' then

if din = “111” then xout <= “11111110”;

elsif din = “110” then xout <= “11111101”;

elsif din = “101” then xout <= “11111011”;

elsif din = “100” then xout <= “11110111”;

elsif din = “011” then xout <= “11101111”;

elsif din = “010” then xout <= “11011111”;

elsif din = “001” then xout <= “10111111”;

else xout <= “11111011”;

end if;

end process;

end one;